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dsPIC30F4011/4012

DS70135G-page 162

2010 Microchip Technology Inc.

Any interrupt that is individually enabled (using the

corresponding IE bit) and meets the prevailing priority

level can wake-up the processor. The processor

processes the interrupt and branches to the ISR. The

SLEEP status bit in the RCON register is set upon

wake-up.

All Resets wake-up the processor from Sleep mode.

Any Reset, other than POR, sets the SLEEP status bit.

In a POR, the SLEEP bit is cleared.

If Watchdog Timer is enabled, the processor wakes-up

from Sleep mode upon WDT time-out. The SLEEP and

WDTO status bits are both set.

21.5.2

IDLE MODE

In Idle mode, the clock to the CPU is shut down while

peripherals keep running. Unlike Sleep mode, the clock

source remains active.

Several peripherals have a control bit in each module,

that allows them to operate during Idle.

LPRC Fail-Safe Clock Monitor remains active if clock

failure detect is enabled.

The processor wakes up from Idle if at least one of the

following conditions is true:

Any interrupt that is individually enabled (IE bit is

‘1’) and meets the required priority level

Any Reset (POR, BOR, MCLR)

WDT time-out

Upon wake-up from Idle mode, the clock is re-applied

the

CPU

and

instruction

execution

begins

immediately, starting with the instruction following the

PWRSAV

instruction.

Any interrupt that is individually enabled (using IE bit)

and meets the prevailing priority level can wake-up the

processor. The processor processes the interrupt and

branches to the ISR. The IDLE status bit in RCON

Any Reset, other than POR, sets the IDLE status bit.

On a POR, the IDLE bit is cleared.

If Watchdog Timer is enabled, then the processor

wakes-up from Idle mode upon WDT time-out. The

IDLE and WDTO status bits are both set.

Unlike wake-up from Sleep, there are no time delays

involved in wake-up from Idle.

21.6

Device Configuration Registers

The Configuration bits in each device Configuration

programmed by a device programmer, or by using the

In-Circuit Serial Programming (ICSP) feature of the

device. Each device Configuration register is a 24-bit

used to hold configuration data. There are five device

Configuration registers available to the user:

FOSC (0xF80000): Oscillator Configuration

FWDT (0xF80002): Watchdog Timer

Configuration Register

FBORPOR (0xF80004): BOR and POR

Configuration Register

FGS (0xF8000A): General Code Segment

Configuration Register

FICD (0xF8000C): Debug Configuration

The placement of the Configuration bits is automatically

handled when you select the device in your device

programmer. The desired state of the Configuration bits

may be specified in the source code (dependent on the

language tool used), or through the programming

interface. After the device has been programmed, the

application software may read the Configuration bit

values through the table read instructions. For additional

information,

please

refer

the

programming

specifications of the device.

Note:

In spite of various delays applied (TPOR,

TLOCK and TPWRT), the crystal oscillator

(and PLL) may not be active at the end of

the time-out (e.g., for low-frequency crys-

tals). In such cases, if FSCM is enabled,

the device detects this condition as a

clock failure and processes the clock fail-

ure trap. The FRC oscillator is enabled,

and the user must re-enable the crystal

oscillator. If FSCM is not enabled, then the

device simply suspends execution of code

until the clock is stable and remains in

Sleep until the oscillator clock has started.

Note:

If the code protection Configuration fuse

bits

(FGS<GCP>

and

FGS<GWRP>)

have been programmed, an erase of the

entire

code-protected

device

only

possible at voltages VDD

≥ 4.5V.

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